1. Field of the Invention
The invention is generally directed to the field of solid state materials. The invention is more specifically directed to new ways of growing single-crystal, solid state films on relatively arbitrary substrates that are nucleation-unfriendly.
2a. Cross Reference to Co-Related Applications
The following copending U.S. patent applications are fully owned by the owner of the present application, and their disclosures are incorporated herein by reference:
(A) Ser. No. 09/025,724 [Attorney Docket No. SAXN8000DIV1] filed Feb. 18, 1998 by inventor Arjun N. Saxena and originally entitled, ADVANCED TECHNIQUE TO GROW SINGLE CRYSTAL FILMS ON AMORPHOUS AND/OR NON-SINGLE CRYSTAL SURFACES; and
(B) Ser. No. 08/140,723 [Attorney Docket No. SAXN8000] filed Oct. 21, 1993 by inventor Arjun N. Saxena and originally entitled, ADVANCED TECHNIQUE TO GROW SINGLE CRYSTAL FILMS ON AMORPHOUS AND/OR NON-SINGLE CRYSTAL SURFACES (which application is scheduled to issue as U.S. Pat. No. 5,792,270 on Aug. 11, 1998).
2b. Cross Reference to US Patents
The following U.S. patents are incorporated herein by reference:
(A) U.S. Pat. No. 5,472,508, issued Dec. 5, 1995 to Arjun N. Saxena, entitled APPARATUS FOR SELECTIVE CHEMICAL VAPOR DEPOSITION OF DIELECTRIC, SEMICONDUCTOR AND CONDUCTIVE FILMS ON SEMICONDUCTOR AND METALLIC SUBSTRATES; and
(B) U.S. Pat. No. 4,686,758, issued Aug. 18, 1987 to M. S. Liu and B. Hoefflinger, entitled THREE-DIMENSIONAL CMOS USING SELECTIVE EPITAXIAL GROWTH.
2c. Cross Reference to Related Other Publications
The following publications are believed to be related to the present application and are cited here for purposes of reference:
(a) G. E. Moore, "Lithography and the Future of Moore's Law", Optical/Laser Microlithography VIII: Proceedings of the SPIE, 2440, Feb. 20, 1995, pp. 2-17;
(b) M. L. Alles, "Thin-film SOI emerges", IEEE Spectrum, June 1997, pp. 37-45;
(c) A. N. Saxena, K. Ramkumar, S. K. Ghosh, and M. A. Bourgeois, "Technology and Reliability Issues of Multilevel Interconnects in Bipolar, BiCMOS and CMOS VLSIC/ULSIC", Pro. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), Minneapolis, Minn., 1993, pp. 12-19; and
(d) K. Yamagata, "Method for Forming Crystal Layers on a Substrate", European Patent Application No. 89302983.5, fled 23/03/89, published 02/11/89, Bulletin 89/44.
3. Background
Introduction
Characteristics of solid state materials can vary substantially depending on whether various atoms of a solid state composition are distributed in a highly ordered manner, or in a highly random manner or in some semi-ordered manner between these extremes.
The order-dependent characteristics of solid state materials can include one or more of the following: (a) electrical conductivity and other electrical properties (e.g., dielectric constant, charge mobility, etc.); (b) optical conductivity and other optical properties (e.g., refractive index, photon speed, etc.); (c) thermal conductivity and other thermal properties (e.g., coefficient of thermal expansion, etc.); (d) mechanical strength and other mechanical properties (e.g., stress/strain curves, etc.); and chemical properties (e.g., resistance to corrosion, reaction consistency, etc.).
If practical processes can be developed for creating tightly-knit combinations of highly ordered materials and of other materials whose atoms are organized in a more random fashion, new composites of solid state materials may be created that have useful combinations of complex characteristics. For example, it may be desirable to integrate optical single-crystal materials with semiconductor single-crystal materials so as to provide integrated monolithic devices with both kinds of functionalities (e.g., output and/or detection and/or processing of electrical signals as well as output and/or detection and/or processing of optical signals).
The term, `single-crystal` (sc) or `monocrystalline` (mono) is generally applied to a solid state article, layer or other entity whose atoms maintain a regular pattern of organization repeatedly and three-dimensionally over application-dictated linear distances. In most instances, these application-dictated linear distances cover at least 100 atoms, if not at least thousands or millions of atoms in at least one direction. For lithographically-defined devices having critical dimension of no smaller than about 0.1 .mu.m, the application-dictated definition of single-crystal may be considered to cover 0.1 .mu.m in at least one linear direction (typically laterally across an integrated circuit substrate). Examples of single-crystal materials include diamond, quartz, and monocrystalline silicon such as used in integrated circuits.
Traditionally, single-crystal materials are either found in nature or are manufactured by growth from a single-point `seed`. Single-crystal materials may also be grown by way of homogeneous epitaxy atop a substrate made of the same single-crystal material. Single-crystal materials may be further grown by way of heterogeneous epitaxy atop a substrate made of a different single-crystal material that happens to have similar lattice constants (e.g., a GaAlAs layer grown on a GaAs monocrystalline substrate).
In the semiconductor industry, cylindrically-shaped silicon ingots are examples of seed-grown, monocrystalline silicon. These are typically sliced into disk shaped wafers. Often, a near-perfect, layer of single-crystal silicon is epitaxially grown on the original, monocrystalline wafer to serve as an active layer for electronic components (e.g., transistors). Plural integrated circuits are then lithographically defined on or in the active layer of each wafer, with one or more such circuits being placed in respective reticle areas. The wafer is then cut into individual dice and each die becomes a `chip` that is sealed into a corresponding IC package.
The term `amorphous` (am) is generally applied to solid state materials whose atoms are arranged in a highly chaotic or random manner. Examples of amorphous materials include non-crystalline, common glass (typically composed of amorphous silicon dioxide in combination with oxides of other materials such as boron, aluminum, sodium, zinc, etc.), and graphite or charcoal (amorphous carbon). Silicon may also be obtained in amorphous form.
It is possible to have crystal-like orderliness on a small atomic scale of, say, linear distances covering only a few hundred atoms while the same orderliness is not maintained over greater distances of say about 0.1 .mu.m or greater. Materials having this type of mixed organization are often referred to as `polycrystalline` (poly). Silicon may be obtained in a polycrystalline form, such as when Si is deposited by CVD process on amorphous Sio.sub.2.
The usefulness of single-crystal (mono-crystalline) materials is well known. By way of example, monocrystalline silicon substrates are used extensively in the microelectronics industry as explained above. A major problem, however, is how to economically manufacture plural layers of monocrystalline silicon and how to combine these to other layers of different materials such as amorphous insulators. Although it well known how to produce a layer of polycrystalline Si on top of a layer of amorphous SiO.sub.2 or amorphous Si.sub.3 N.sub.4, the provision of single-crystal Si on top of amorphous SiO.sub.2 or amorphous Si.sub.3 N.sub.4 is a completely different matter. Heretofore, it was not known how to economically grow single-crystal materials on top of amorphous or other nucleation-unfriendly solids.
The Role of Single-Crystal Materials in the Semiconductor Industry
The current silicon-based, integrated circuit business has a total world market value in excess of $100 billion and continues to grow rapidly as new applications are created for computer chips and the like. Because of manufacturing limitations in the prior art, the `active` part of most IC's is manufactured as a single, two-dimensional entity that is disposed across the planar surface of a single monocrystalline substrate. Mass production realities limit the size of each IC substrate to that of industry-standard dice and IC packages. (Each die is cut from a standard-sized wafer (e.g., one having a 300 mm diameter) after circuits are fabricated on the wafer. A typical die is about 20 mm by 30 mm or smaller.) The limited surface area that is available on each single-crystal, two-dimensional plane places a constraint on the number of active devices such as transistors, diodes, etc., that may be laid out on or in the substrate. Typically, the active monocrystalline layer is epitaxially grown on the monocrystalline surface of the wafer and later diced out. Each die has the same crystal orientation ((100), (111), etc.) as that of the bulk wafer.
In order to reproduce integrated circuit chips on a mass production scale so that each chip has substantially same and good characteristics, it is desirable that the crystal structure of the epitaxial layer should be as near perfect as possible, with as few defects as possible. This goal has been generally achieved through the use of annealing and other crystal-perfecting techniques. It is the primary reason that the microelectronics industry has been able to continue to grow rapidly according to Moore's Law. It is desirable to continue the growth trend predicted by Moore's Law. However, many obstacles stand in the way.
Moore's Law predicts that transistor size will continue to shrink and the number of transistors on an integrated circuit die will double approximately every 18 months. This predictive law assumes that integrated circuits may only be laid out in a two-dimensional manner on one monocrystalline plane of silicon. Those skilled in the art recognize that the shrinkage of transistor size may not be able to go on forever. Eventually, fundamental limits of either the interconnect or transistor physics and economic realities will bring the shrinkage to a halt. While no definite limit has yet been established, it appears that a fundamental limit will be hit as transistors approach channel lengths of about 0.1 .mu.m.
To overcome this expected problem, artisans are exploring ways to increase the amount of active surface area in each IC chip. Some practitioners have tried to extend the amount of surface area available to active devices by forming so-called thin-film transistors (TFT) in polysilicon layers of an integrated circuit chip. The polysilicon layers are deposited on insulating silicon dioxide layers, above the base monocrystalline layer of silicon. Unfortunately, the thin-film transistors of such polysilicon layers generally have poor electrical characteristics and poor reproducibility from one chip to the next. This is primarily due to the random distribution of polycrystalline grains of different crystal orientations within the drain, source and channel regions of each transistor. Also, there is the problem that doped polycrystalline silicon tends to have a substantially higher electrical resistance (about 15 .OMEGA./square) than does doped monocrystalline silicon (about 5 .OMEGA./square).
Another approach for extending the usable surface area of monocrystalline silicon is known in the industry as ELO (Epitaxial Lateral Overgrowth). Here, windows are created through a gate oxide or other oxide layer of the device to expose the underlying monocrystalline substrate. The exposed substrate area is then used as a seed for epitaxially growing new single-crystal material. The epitaxial material grows to extend through the window and to continue out onto the overlying amorphous silicon dioxide. This ELO technique has met with only limited success. One drawback of ELO is that it consumes part of the precious surface area of the monocrystalline substrate for seeding purposes and thereby works against its primary goal of increasing available area. Another drawback of ELO is that this form of monocrystalline growth cannot continue indefinitely. As distance from the seed window increases, there is a greater tendency to form polysilicon instead of single-crystal material.
Another approach worth mentioning is one called wafer bonding. Here, two or more monocrystalline wafers are bonded together for the purpose of increasing the available area of monocrystalline silicon within an integrated circuit package. However, this technique is burdened with problems relating to aligning the bonded wafers and forming interconnect between one wafer and the next. The wafer bonding process does not provide economies of scale in a mass production environment in the same, cost-effective way as do the more traditional methods for forming circuits on a monolithic substrate.
Another technology that is worth noting is one that creates so-called SOI (silicon-on-insulator) by means of a SIMOX process (separation by implantation of oxygen). Here, oxygen atoms are implanted at high energy and high dose to form a silicon dioxide insulating layer between the upper portion of an originally single-crystal substrate and the bottom bulk portion of the same substrate. Thermal annealing at high temperatures (e.g., 1000-1300.degree. C.) is used to try to cure defects created in the upper crystal layer by the implantation therethrough of the oxygen atoms. SIMOX devices have the advantage of being able to operate at higher frequencies than devices formed directly on bulk substrate because the buried insulation layer reduces parasitic capacitance. However, the SIMOX process is relatively expensive due to the high costs of implanting the oxygen atoms and curing the implant-induced defects.
Another physical limit that is impeding progress in microelectronics is that of transistor switching speed. Charge carriers in monocrystalline silicon have limited mobility. Other materials exhibit higher mobilities and hence promise faster switching speeds. Because of this, practitioners have attempted to fabricate transistors using more exotic materials such as III-V semiconductor compounds (e.g., GaAs, GaAlAs, GaP, etc.) and II-VI compounds. These attempts have met with only limited success because of the difficulty of controlling the distribution of atoms within these materials on a reproducible basis from one chip to the next. It would be highly advantageous if the atomic organization of such exotic materials could be reproduced on a mass production basis from one chip to the next. The resulting, single-crystal III-V and II-VI materials may then be used to mass produce devices that operate at microwave frequencies. Additionally, if single-crystal forms of III-V and II-VI compounds could be created monolithically and economically in a same monolith that contains monocrystals of more traditional, column IV materials (e.g., Ge, Si, SiGe), then practitioners would be able to integrate more traditional Si/Ge-based circuits (e.g., microprocessor cores, memory cores, TTL interfaces, etc.) with higher frequency circuitry that relies on single-crystal forms of III-V and/or II-VI compounds. This would open up whole new possibilities in coupling slower-speed logic circuitry with higher-frequency communications circuitry.
It has been proposed that ultimately, as signal processing and communications speeds increase beyond the capabilities of purely-electronic devices that such operations may be taken over in part or in whole by optical devices. As is known, the utility of silicon is limited in optical applications because of silicon's indirect band gap. On the other hand, many III-V and/or II-VI compounds do not suffer from such limitations and can be used to provide optical functions such as photon detection, optical output and optical signal processing over a wide spectrum that covers at least the infrared through deep UV range. It would be highly advantageous if single-crystal forms of optically-active III-V and II-VI compounds could be created monolithically and economically integrated in a same monolith that contains monocrystals of more traditional, column IV materials (e.g., Ge, Si, SiGe) as well as single-crystal forms of electronically-active III-V and II-VI compounds. This would open up whole new possibilities in coupling slower-speed logic circuitry with higher-frequency communications circuitry and yet-higher speed optical systems. For example, more traditional forms of Si/Ge-based circuits (e.g., microprocessor cores, memory cores, TTL interfaces, etc.) could be coupled to high bandwidth optical communications systems that operate using single-crystal forms of III-V and/or II-VI compounds to provide integrated control and communications capabilities.
The Role of Single-Crystal Materials in the Other Industries
The use of single-crystal semiconductors in the semiconductor industry constitutes only the tip of the iceberg with regard to the general usefulness of single-crystal solid state materials. The superior mechanical hardness and other properties of many single-crystal materials may be used to improve the wearability and other characteristics of many products. For example, if it were possible to economically form single-crystal films such as made of diamond or Al.sub.2 O.sub.3 or SnO.sub.2, these might be used to provide improved tribology (low friction mechanical interfaces); more chemically-inert surfaces such as may be practical in medical applications; more thermally conductive packagings such as may be useful in electronics and other industries; and many other improved functionalities. In addition to formation of single-crystal semiconductors and single-crystal insulators, it is also often advantageous to form single-crystal metals and single-crystal superconducting compositions. The range of useful applications for such materials can include aerospace, optical, medical, machine tools, tribology and electronics. Some examples of single-crystal materials that may be advantageously formed in combination with non-single crystal materials include diamond, Al.sub.2 O.sub.3, SnO.sub.2, SiC, TiN, Ti, Hf, Zr, Cu, etc.